STA Engineer (Static Timing Analysis Engineer)

Education: BE/B Tech or ME/M Tech in CSE & ECE or related stream

Experience: 5+ years  

Primary Skills:
1) Should have performed timing analysis, validation, and debugging across various PVT (Process, Voltage, Temperature) corners using Tempus.
2) Hands-on experience with Tempus DMMMC flow for Static Timing Analysis (STA) is a must.
3) Involved in STA setup, convergence, reviews, and sign-off for both scan and functional modes.
4) Analyzed timing reports and reviewed unconstrained endpoints to ensure comprehensive coverage.
5) Strong expertise in STA methodologies with a solid understanding of noise, crosstalk, and On-Chip Variation (OCV) effects.
6) Experienced in timing closure at both block and full-chip levels for advanced process nodes such as 22nm, 16nm, and 5nm.

Secondary Skills:
1) Collaborated closely with design, synthesis, and PNR teams to provide feedback and drive smooth timing closure.
2) Proficient in scripting with Tcl and Python for STA automation and analysis.
3) Familiar with Cadence-based STA flows.
4) Prior experience working on power-domain-based designs is an added advantage.

Work Location: Bengaluru/Bangalore 

Interview Mode: F2F